? semiconductor components industries, llc, 2001 june, 2001 rev. 5 1 publication order number: mc100ept24/d mc100ept24 3.3vlvttl/lvcmos to differential lvecl translator the mc100ept24 is a lvttl/lvcmos to differential lvecl translator. because lvecl levels and lvttl/lvcmos levels are used, a 3.3 v, +3.3 v and ground are required. the small outline 8lead package and the single gate of the ept24 makes it ideal for those applications where space, performance, and low power are at a premium. ? 350 ps typical propagation delay ? maximum frequency > 1.0 ghz typical ? the 100 series contains temperature compensation ? operating range: v cc = 3.0 v to 3.6 v; v ee = 3.6 v to 3.0 v; gnd = 0 v ? pnp lvttl inputs for minimal loading ? q output will default high with input open device package shipping ordering information mc100ept24d so8 98 units / rail mc100ept24dr2 so8 mc100ept24dt tssop8 100 units / rail mc100ept24dtr2 tssop8 http://onsemi.com *for additional information, see application note and8002/d marking diagrams* a = assembly location l = wafer lot y = year w = work week alyw kpt24 alyw ka24 2500 tape & reel 2500 tape & reel so8 d suffix case 751 1 8 tssop8 dt suffix case 948r 1 8 1 8 1 8
mc100ept24 http://onsemi.com 2 1 2 3 45 6 7 8 q gnd v cc figure 1. 8lead pinout (top view) and logic diagram d q nc nc v ee lvttl lvecl pin description pin q, q d lvttl input function differential lvecl outputs v cc gnd ground positive supply v ee negative supply nc no connect attributes characteristics value internal input pulldown resistor n/a internal input pullup resistor n/a esd protection human body model machine model charged device model > 4 kv > 200 v > 2 kv moisture sensitivity, indefinite time out of drypack (note 1.) level 1 flammability rating oxygen index ul94 code v0 a 1/8o 28 to 34 transistor count 181 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. maximum ratings (note 2.) symbol parameter condition 1 condition 2 rating units v cc positive power supply gnd = 0 v v ee = 3.3 v 3.8 v v ee negative power supply gnd = 0 v v cc = +3.3 v 3.8 v v in p ut voltage gnd 0 v v v 0tov v v in input voltage gnd = 0 v v i v cc 0 to v cc v i out output current continuous surge 50 100 ma ma ta operating temperature range 40 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 8 soic 8 soic 190 130 c/w c/w q jc thermal resistance (junction to case) std bd 8 soic 41 to 44 c/w q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 8 tssop 8 tssop 185 140 c/w c/w q jc thermal resistance (junction to case) std bd 8 tssop 41 to 44 c/w t sol wave solder <2 to 3 sec @ 248 c 265 c 2. maximum ratings are those values beyond which device damage may occur.
mc100ept24 http://onsemi.com 3 lvttl input dc characteristics v cc = 3.3 v, v ee = 3.6 v to 3.0 v, gnd= 0.0 v; t a = 40 c to 85 c symbol characteristic condition min typ max unit i ih input high current v in = 2.7 v 20 m a i ihh input high current v in = 6.0 v 100 m a i il input low current v in = 0.5 v 0.6 ma v ik input clamp diode voltage i in = 18 ma 1.2 v v ih input high voltage 2.0 v v il input low voltage 0.8 v necl output dc characteristics v cc = 3.3 v, v ee = 3.3 v, gnd= 0.0 v (note 3.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit v oh output high voltage (note 4.) -1145 1020 -895 -1145 1020 -895 -1145 1030 -895 mv v ol output low voltage (note 4.) -1945 1820 -1695 -1945 1820 -1695 -1945 1820 -1695 mv i cc power supply current 2.0 4.0 2.0 4.0 2.0 4.0 ma i ee power supply current 20 30 38 20 30 38 20 30 38 ma note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 3. output levels will vary 1:1 with gnd. v ee can vary 0.3 v. 4. outputs are terminated through a 50 ohm resistor to gnd2 volts. ac characteristics v cc = 3.0 v to 3.6 v, v ee = 3.6 v to 3.0 v, gnd= 0.0 v (note 5.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum frequency (see figure 2. f max /jitter) > 1 > 1 > 1 ghz t plh , t phl propagation delay to output differential (note 6.) 300 500 800 300 530 800 300 560 800 ps t jitter cycletocycle jitter (see figure 2. f max /jitter) 0.2 < 1 0.2 < 1 0.2 < 1 ps t r t f output rise/fall times q, q (20% 80%) 70 125 170 80 130 180 100 150 200 ps 5. measured using a 750 mv source, 50% duty cycle clock source. all loading with 50 ohms to v cc 2.0 v. 6. specifications for standard ttl input signal.
mc100ept24 http://onsemi.com 4 0 100 200 300 400 500 600 700 800 900 100 300 500 700 900 1100 1300 1500 1 2 3 4 5 6 7 8 9 figure 2. f max /jitter frequency (mhz) (jitter) v outpp (mv) jitter out ps (rms) v tt = v cc 2.0 v driver device receiver device q qb d db 50 50 v tt figure 3. typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.)
mc100ept24 http://onsemi.com 5 resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1503 eclinps i/o spice modeling kit an1504 metastability and the eclinps family an1560 low voltage eclinps spice modeling kit an1568 interfacing between lvds and ecl an1596 eclinps lite translator elt family spice i/o model kit an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8020 termination of ecl logic devices for an updated list of application notes, please see our website at http://onsemi.com.
mc100ept24 http://onsemi.com 6 package dimensions so8 d suffix plastic soic package case 75107 issue w seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 x y g m y m 0.25 (0.010) z y m 0.25 (0.010) z s x s m dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 2.90 3.10 0.114 0.122 c 0.80 1.10 0.031 0.043 d 0.05 0.15 0.002 0.006 f 0.40 0.70 0.016 0.028 g 0.65 bsc 0.026 bsc l 4.90 bsc 0.193 bsc m 0 6 0 6 seating plane pin 1 1 4 85 detail e b c d a g detail e f m l 2x l/2 u s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) t v w 0.25 (0.010) 8x ref k ident k 0.25 0.40 0.010 0.016 tssop8 dt suffix plastic tssop package case 948r02 issue a notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. terminal numbers are shown for reference only. 6. dimension a and b are to be determined at datum plane -w-.
mc100ept24 http://onsemi.com 7 notes
mc100ept24 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc100ept24/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
|
